1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a synchronous semiconductor memory device performing an operation in response to an external clock signal.
2. Description of the Prior Art
A synchronous semiconductor memory device developed for high-speed access executes every operation (instruction) necessary for reading or writing data in synchronization with a clock (external clock signal) supplied from the exterior in a stable cycle.
The structure of a principal part of a conventional synchronous semiconductor memory device 9000 is now described with reference to FIG. 11.
The conventional synchronous semiconductor memory device 9000 shown in FIG. 11 comprises a plurality of banks (FIG. 11 representatively shows a bank B0), an output stage 10 and an output control circuit 20.
The synchronous semiconductor memory device 9000 further comprises an internal clock generation circuit (not shown) for generating an internal clock signal synchronous with an external clock signal, for reading data from the bank B0 in synchronization with the internal clock signal when a read instruction is inputted from the exterior. The output stage 10 outputs the data read from the bank B0 to a data input/output terminal DQ on the basis of a signal outputted from the output control circuit 20. A read mask signal (referred to as EXTDQM) inputted from the exterior in such a read operation is adapted to mask (inhibit) output of the data at prescribed timing.
The structure of the output stage 10 is now described. The output stage 10 comprises a first output stage C1, a second output stage C2 and a final output stage C3.
The first output stage C1 includes a preamplifier 11 and a gate circuit 12. Complementary data buses RDA and ZRDA connect the preamplifier 11 and the gate circuit 12 with each other. The preamplifier 11 amplifies the data read from the bank B0. The gate circuit 12 outputs the data received from the preamplifier 11 to complementary data buses RDF and ZRDF in response to a gate control signal ZBEST(0).
When four banks are provided, data read from the remaining banks (not shown) are transferred to the complementary data buses RDF and ZRDF in response to gate control signals ZBEST(1), ZBEST(2) and ZBEST(3) outputted from the output control circuit 20 respectively. In other words, the data outputted from any bank are selectively transferred to the complementary data buses RDF and ZRDF in response to any of the gate control signals ZBEST(0), ZBEST(1), ZBEST(2) and ZBEST(3).
The second output stage C2 comprises a gate circuit 13 and a latch circuit 14. The gate circuit 13 fetches the data from the complementary data buses RDF and ZRDF in response to a gate control signal RDGATE. The latch circuit 14 latches the data received from the gate circuit 13 and outputs the same to complementary data buses RD and ZRD.
The final output stage C3 comprises a gate circuit 15 and an output buffer 16. The gate circuit 15 latches the data from the complementary data buses RD and ZRD in response to a gate control signal CLKOEN. The output buffer 16 amplifies the data received from the gate circuit 15 and outputs the same to the data input/output terminal DQ.
The complementary data buses RDF and ZRDF are connected with a P-channel MOS transistor P1. The transistor P1 resets the complementary data buses RDF and ZRDF in response to a reset control signal ZRDFPC.
The complementary data buses RD and ZRDF are connected with a P-channel MOS transistor P2. The transistor P2 resets the complementary data buses RD and ZRD in response to a reset control signal ZRDPC.
The output control circuit 20 is now described.
The output control signal 20 generates various signals for controlling the flow of the data in the output stage 10. FIG. 11 representatively illustrates a reset signal generation circuit 21, a gate control signal generation circuit 22, a reset signal generation circuit 23, a gate control signal generation circuit 24 and an output control signal generation circuit 25.
The reset signal generation circuit 21 outputs the reset signal ZRDFPC for controlling the ON/OFF state of the transistor P1. The gate control signal generation circuit 22 outputs the gate control signal RDGATE for controlling switching of the gate circuit 13. The reset signal generation circuit 23 outputs the reset signal ZRDPC for controlling the ON/OFF state of the transistor P2. The gate control signal generation circuit 24 outputs the gate control signal CLKOEN for controlling switching of the gate circuit 15. The output control signal generation circuit 25 outputs an output enable signal OEM for controlling the operation of the output buffer 16.
The circuit structures of the output control signal generation circuit 25 and the final output stage C3 are now described with reference to FIG. 12.
The final output stage C3 is first described. As shown in FIG. 12, the gate circuit 15 includes NAND circuits N3, N4, N5 and N6 and an invertor circuit I2. The NAND circuit N4 is connected with the complementary data buses RD and ZRD. The NAND circuit N3 receives the gate control signal CLKOEN and a power supply voltage VDD. The invertor circuit I2 inverts and outputs an output of the NAND circuit N3. The NAND circuit N5 is connected with the data bus RD and output nodes of the NAND circuit N4 and the invertor circuit I2. The NAND circuit N6 is connected with the data bus ZRD and the output nodes of the NAND circuit N4 and the invertor circuit I2. The gate circuit 15 transfers the data received from the complementary data buses RD and ZRD to the output buffer 16 in response to the gate control signal CLKOEN.
The output buffer 16 is formed by a driver 17 and a latch circuit 18. The latch circuit 18 includes an invertor circuit I1, NAND circuits N1 and N2, AND circuits A1 and A2 and NOR circuits NR1 and NR2. The latch circuit 18 latches the signal outputted from the gate circuit 15 and outputs the same to complementary data buses DQ0 and ZDQ0. The output enable signal OEM outputted from the output control signal generation circuit 25 controls the operation of the latch circuit 18.
The driver 17 is connected with the complementary data buses DQ0 and ZDQ0. The driver 17 receives the data from the complementary data buses DQ0 and ZDQ0, for amplifying and outputting the result to the data input/output terminal DQ.
The output control signal generation circuit 25 is now briefly described. As shown in FIG. 12, the output control signal generation circuit 25 includes shift circuits 30 and 31, a NAND circuit N19 and an invertor circuit I4.
The shift circuit 31 shifts a signal OEMF by a time responsive to a CAS latency CL and outputs the same (signal OEMST). The CAS latency LC is a value indicating the number of the clock for starting outputting the data after input of a read instruction READ. The signal OEMF, which keeps a high level by a burst length BL (value indicating the number of clocks of read data to be outputted), is generated on the basis of the read instruction READ.
The shift circuit 30 includes NAND circuits N11, N12, N13, N14, N15, N16, N17 and N18. The shift circuit 30 outputs an internal control signal ZDQM in a delay by one clock with respect to an internal clock signal CLK (and an inverted clock signal ZCLK. The internal control signal ZDQM is a negative-phase internal signal corresponding to the read mask signal EXTDQM.
The NAND circuit N19 receives the signal OEMST and the output signal from the shift circuit 30 in its input. The invertor circuit I4 receives an output signal from the NAND circuit N19 in its input, for inverting the same and outputting the result as the output enable signal OEM.
The synchronous semiconductor memory device 9000 successively outputs the data read from the banks to the exterior in a pipeline operation on the basis of the aforementioned reset signal ZRDFPC and ZRDPC, gate control signals ZBEST(0) to ZBEST(3), RDGATE and CLKOEN, and output enable signal OEM.
An operation of the conventional synchronous semiconductor memory device 9000 is now described with reference to a timing chart shown at (A) to (Q) in FIG. 13.
A read operation with reference to the bank B0 is described on the assumption that the CAS latency CL is 3 and the burst length BL is 4. It is assumed that the internal clock signal CLK rises at times t1, t2, t3 . . . . It is also assumed that the synchronous semiconductor memory device 9000 performs the read operation only with respect to the single bank B0 (thus, the gate control signal ZBEST(0) is regularly fixed at a low level). It is further assumed that the read mask signal EXTDQM is inputted at a time t5 (for masking data outputted at a time t7 if the latency is 2).
As shown in FIG. 13, an activation instruction ACT (for activating a word line) is inputted at the time t1 and the read instruction READ is inputted at the time t3, whereby a column selection signal CSL rises to a high level to activate a column system of the bank B0. Thus, first read data (read at the time t3) is transferred to the preamplifier 11, which in turn amplifies this data and transfers the result to the complementary data buses RDF and ZRDF.
Following a time t4, the gate control signal RDGATE goes high at a proper time. Therefore, the latch circuit 14 fetches the data from the complementary data buses RDF and ZRDF. Thus, the latch circuit 14 transfers the first read data from the complementary data buses RDF and ZRDF to the complementary data buses RD and ZRD.
Then, the reset signal ZRDFPC of a low level is generated at a proper time so that the transistor P1 receiving the same in its gate conducts, thereby precharging the complementary data buses RDF, ZRDF, RDA and ZRDA.
Then, a second column selection signal CSL rises to a high level for transferring second read data (read at the time t4) to the preamplifier 11. The preamplifier 11 amplifies the transferred second data and transfers the result to the complementary data buses RDF and ZRDF again.
Following the time t5, the gate control signal CLKOEN goes high at a proper time so that the output buffer 16 fetches the first read data transferred to the complementary data buses RD and ZRD at the time t4.
The data input/output terminal DQ outputs the data (Q0 at (C) in FIG. 13) fetched in the output buffer 16 to the exterior when the output enable signal OEM enters a high-level state.
Then, the reset signal ZRDPC of a low level is generated at a proper time so that the transistor P2 receiving this signal in its gate conducts, thereby precharging the complementary data buses RD and ZRD. Thus, next data can be transferred.
Then, the gate control signal RDGATE goes high at a proper time. Thus, the second read data is transferred from the complementary data buses RDF and ZRDF to the complementary data buses RD and ZRD.
Then, the reset signal ZRDFPC of a low level is generated at a proper time so that the transistor P1 receiving this signal in its gate enters a conducting state, thereby precharging the complementary data buses RDF, ZRDF, RDA and ZRDA.
Then, a third column selection signal CSL goes high for transferring third read data (read at the time t5) to the preamplifier 11. The preamplifier 11 amplifies and transfers the data to the complementary data buses RDF and ZRDF.
At a time t6, the gate control signal CLKOEN goes high, so that the output buffer 16 fetches the second read data transferred to the complementary data buses RD and ZRD.
However, the output enable signal OEM goes low due to the read mask signal EXTDQM inputted at the time t5. Therefore, the second read data, which is to be outputted from the data input/output terminal DQ to the exterior at the time t7, is not outputted.
The same operation is further repeated for outputting data Q0, Q2 and Q3 in correspondence to the first, third and fourth read data except the second read data.
If the CAS latency CL is 2, the complementary data buses RDA and ZRDA, RDF and ZRDF and RD and ZRD perform the same operations in a single cycle. In this case, these complementary data buses RDA and ZRDA, RDF and ZRDF and RD and ZRD are simultaneously precharged.
As hereinabove described, the conventional synchronous semiconductor memory device 9000 can output the data by operating at the timing shown at (A) to (Q) in FIG. 13 in synchronization with the external clock signal supplied from the exterior in a stable cycle.
However, the conventional synchronous semiconductor memory device 9000 disadvantageously outputs data to be masked to the exterior, as described below.
This problem of the conventional synchronous semiconductor memory device 9000 is now described with reference to a timing chart shown at (A) to (J) in FIG. 14.
It is assumed that data are read at times identical to those shown at (A) to (Q) in FIG. 13. The read mask signal EXTDQM is inputted at a time t5.
As shown in FIG. 14, the output enable signal OEM falls from a high level to a low level at a time t6, due to the read mask signal EXTDQM inputted at the time t5. At this fall timing, the output enable signal OEM cannot immediately fall to the low level with respect to the leading edge of the external clock signal EXTCLK, in order to satisfy a data hold tOH (generally 3 ns) of output data. Therefore, the output enable signal OEM must maintain the high level for a period of several ns from the leading edge (time t6) of the external clock signal EXTCLK.
On the other hand, the synchronous semiconductor memory device 9000 must perform the serial transfer operation (pipeline operation) for transferring the data from the complementary data buses RD and ZRD to the output buffer 16, then from the complementary data buses RDF and ZRDF to the complementary data buses RD and ZRD and from the bank B0 to the complementary data buses RDF and ZRDF in a single operation clock. In order to increase the data output speed (operating speed) of the conventional synchronous semiconductor memory device 9000, therefore, the gate control signal CLKOEN must rise as fast as possible so that the output buffer 16 fetches the data at a high speed.
When such requirement is satisfied, however, the output enable signal OEM maintains the high-level state on the trailing edge of the gate control signal CLKOEN (see the output enable signal OEM at the time t6 shown at (D) in FIG. 14). Thus, the output buffer 16 disadvantageously fetches the data to be masked despite the read mask instruction and outputs the same to the exterior (see an output DOUT at the time t6 shown at (J) in FIG. 14).
If the synchronous semiconductor memory device 9000 outputs this data (hereinafter referred to as invalid data), which must not be outputted from the first, to the exterior, a malfunction is disadvantageously caused in a system receiving the invalid data.